Advanced semiconductor devices increasingly require more complex wiring schemes to wire together individual elements into circuits. These schemes rely on multilevel structures formed from wiring levels containing conductive wires and interconnect levels containing conductive vias that connect conductive wires on two different wiring levels together.
Fabrication of such multilevel structures often requires the use of a fabrication technique called chemical-mechanical-polishing (CMP) of the wiring levels and the interconnect levels. However CMP can cause variations in the flatness of the top surface of semiconductor devices severe enough to effect the quality of the photolithographic process steps used to define the patterns of wires and vias in the wiring and interconnect levels. Variations in flatness occur most frequently on the wiring levels and are caused by differences in conductive wire densities from region to region on the surface semiconductor level being then fabricated. This creates differences in polish rate so more or less material is removed from one region than another. In an attempt to solve this problem, methods have been developed that distribute fill shapes, formed at the same time and of the same material as the conductive wires, in such a manner as to attempt to keep the density of conductive material and therefore the polishing rate, the same in all regions. Fill shapes are isolated from the conductive wires and do not carry electrical signals or power. Fill shapes are added to the design data during the design process.
FIG. 1 is a cross-sectional partial view through the wiring and interconnect levels of a semiconductor die illustrating the placement of fill shapes as presently practiced. Semiconductor device 1 is comprised of substrate 10 and via levels 20, 40, 60, 80, 100, and 120 alternating with wiring levels 30, 50, 70, 90, 110, and 130. Passivation level 140 seals the device. Wiring levels 50, 70, 90, 110, and 130, in addition to having conductive wires also have fill shapes. Fill shapes are designated by the letter "F" in order to more easily distinguish them for the reader. Fill shapes are conductive as well. Conductive level 50 has conductive wire 50A and fill shapes 52A through 52H. Conductive level 70 has conductive wires 70A through 70C and fill shapes 72A and 72B. Conductive level 90 has conductive wire 90A and 90B and fill shapes 92A through 92F. Conductive level 110 has conductive wire 110A and 110B and fill shapes 112A through 112C. Conductive level 130 has conductive wires 130A and 130B and fill shapes 132A through 132D. Via level 20 has vias 20A through 20C connecting conductive wire 30A with substrate 10 and vias 20D and 20E connecting conductive wire 30B with substrate 10. Via level 40 has via 40A connecting conductive wire 30B with conductive wire 50A. Via level 60 has via 60 A connecting conductive wire 50A with conductive wire 70C. Via level 80 has via 80A connecting conductive wire 70A with conductive wire 90A. Via level 100 has via 100A connecting conductive wire 90A with conductive wire 110A and via 100B connecting conductive wire 90B with conductive wire 110B. Via level 120 has via 120A connecting conductive wire 110A with conductive wire 130A and via 120B connecting conductive wire 110B with conductive wire 130B. All the conductive wires, vias, and fill shapes are held in a matrix of insulator 15 which may be the same insulating material or a different insulating material level to level.
In general insulators are optically transparent or semitransparent while conductors are not in the thickness' used in semiconductor devices. As may be readily seen from FIG. 1, the placement of fill shapes of each of the wiring levels has been done independent of any other level so that when doing a visual inspection fill shapes on higher levels can block line of sight views to the lower wiring and interconnect levels of the device, limiting the usefulness of visual inspection for cause of fail or reliability assessment. For example, in FIG. 1, only conductive wires 130A, 130B and 110A are directly visible, fill shapes 112A, 112B, 112C, and 92F blocking the line of sight from the top surface.
Additionally, should electrical probing of lower levels be desired, the fill shapes block direct access to the lower levels either forcing removal of higher levels and subsequent loss of some or all of the device functionality or the milling of an access hole through the dielectric 15 and fill shapes in the path with the problematic differing etch/mill rates associated with the differing materials. For example, in, FIG. 1, if it was desired to contact conductive wire 70C, levels 140, 130, 120, 110, 110, 90, and 80 would need to be removed.